1. Field of the Invention
The present invention relates to the field of computer systems. More specifically, the present invention relates to scaling of central processing unit (CPU) and system bus clock frequencies of computer systems.
2. Background Information
Scalability of a system product line is often critical to its success. Superior scalability allows a system product line to have multiple models optimized for different performance design points over a wide performance spectrum to be cost effectively manufactured. Additionally, purchasers may start with the lower cost low end performance models, and grow their systems as their computing requirements increase.
Thus, a well designed modern server system often would offer a choice for the number of CPUs to be employed. Many of these well designed server systems also would offer a choice or choices for the CPU clock frequency or frequencies. In order to accommodate the different potential CPU clock frequencies, the system bus would be designed to operate in one of a number of complementary clock frequencies. The selection of the CPU and system bus clock frequencies would be predetermined and set via jumpers.
Under this prior art approach, changing the CPU and system bus clock frequencies would require the jumpers to be reset, a task typically performed by a skilled technician. As the rate of CPU clock frequency improvement continues to outpace the system bus clock frequency, the requirement to maintain certain ratio or ratios between the CPU clock frequency or frequencies and the system bus clock frequency further complicates the task. As the choices for CPU and system bus clock frequencies as well as the number of CPUs included in a system increase, the large number of possible combinations from which the optimal selection must be chosen has made the task extremely difficult to be performed manually.
For example, if a server system would allow the employment of 1-4 CPUs having 1-2 clock frequencies to be selected from 3 clock frequencies (e.g. 100, 180, 200 MHz), and a system bus having a clock frequency to be selected from 3 other clock frequencies (e.g. 50, 60 and 66 MHz), with the ratio of any CPU clock frequency to system bus clock frequency to be one of 4 choices (2:1, 3:1, 4:1, and 5:1), the optimal selection will have to made from almost 100 possible combinations.
Thus, it is desirable to have a more efficient and a more reliable way for selecting an optimal system bus clock frequency for a highly scalable computer system. As will be disclosed in more detail below, the present invention achieves these and other desired results.